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Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Volumn , Issue , 2007, Pages 157-160

Power testing of an FPGA based system using modelsim code coverage capability

(3) Arshak, Khalil a Jafer, Essa a Ibala, Christian b

a UNIVERSITY OF LIMERICK (Ireland)

b XILINX INC (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; CODES (STANDARDS); CODES (SYMBOLS); COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; ELECTRON TUBES; ENERGY POLICY; ESTIMATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; HEALTH; INTEGRATED CIRCUITS; MARINE BIOLOGY; NETWORKS (CIRCUITS); TRANSMITTERS;

(MIN ,MAX ,+) FUNCTIONS; AVERAGE POWER CONSUMPTIONS; CAD TOOLS; CODE COVERAGE; DEVICE DATA; ELECTRONIC CIRCUITS; ENERGY CONSUMPTION; ENERGY ESTIMATION; FIELD PROGRAMMABLE GATE ARRAY (FPGA); FIELD PROGRAMMABLE GATE ARRAYS (FPGA) DESIGN; FPGA VENDORS; GLUE LOGIC; HEALTH-MONITORING; LOGIC PARTITIONING; MODELSIM; POWER CONSUMPTION (CE); POWER-PERFORMANCE; RESOURCE UTILIZATIONS; SYSTEM-ON-CHIP (SOC) DESIGNS; TARGET DESIGNS; TELEMETRY SYSTEMS; TEST BENCHES; TRANSITION (JEL CLASSIFICATIONS:E52 ,E41 ,E31); TRANSMITTER AND RECEIVER (TRX); VERILOG;

LOGIC CIRCUITS;

EID: 46449108302 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/DDECS.2007.4295273 Document Type: Conference Paper

Times cited : (7)

References (7)

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2
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3
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4
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- Power Estimation For Field Programmable Gate Arrays, Ph.D Thesis, department of Electrical and Computer Engineering, University of British Colombia, Vancouver BC, Canada
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- (1999)
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5
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6
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- Dynamic Power Consumption in VIRTEX-II FPGA Family
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7
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- (2003) ISPLED'03
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.