Low-power/high-performance explicit-pulsed flip-flop using static latch and dynamic pulse generator

IEE Proceedings: Circuits, Devices and Systems

Volumn 153, Issue 3, 2006, Pages 253-260

  Phyu, M W ^a   Goh, W L ^a   Yeo, K S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; PULSE GENERATORS; SYSTEMS ANALYSIS; TRIGGER CIRCUITS; ULSI CIRCUITS;

DYNAMIC PULSE GENERATOR; LOW-POWER/HIGH-PERFORMANCE EXPLICIT-PULSED FLIP-FLOP; SINGLE EDGE-TRIGGERED FLIP-FLOP (SETFF); STATIC LATCH;

FLIP FLOP CIRCUITS;

EID: 33745306242     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20050163     Document Type: Article

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