Physical defect modeling for fault insertion in system reliability test

Proceedings - International Test Conference

Volumn , Issue , 2009, Pages

  Zhang, Zhaobo ^a   Wang, Zhanglei ^b   Gu, Xinli ^b   Chakrabarty, Krishnendu ^a  

^a Duke University   (United States)

^b CISCO SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL MODIFICATION; ARCHITECTURAL SOLUTIONS; CURRENT SYSTEM; DEFECT MODELING; DELAY DEFECTS; FAULT INSERTION; HARDWARE FAULTS; INDUSTRIAL CIRCUITS; LARGE SYSTEM; OPTIMIZATION TECHNIQUES; PHYSICAL DEFECTS; SIMULATION FRAMEWORK; SINGLE EVENT UPSETS; SYSTEM RELIABILITY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DEFECTS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MODELS; PROGRAM DIAGNOSTICS; TESTING;

QUALITY ASSURANCE;

EID: 76549128523     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2009.5355715     Document Type: Conference Paper

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