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Volumn 45, Issue 8, 1996, Pages 974-979

System dependability evaluation via a fault list generation algorithm

Author keywords

Error injection; Fault injection; Latency; Simulation; VHDL

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; ERROR ANALYSIS; HIGH LEVEL LANGUAGES; RANDOM PROCESSES;

EID: 0030212598     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.536240     Document Type: Review
Times cited : (19)

References (20)
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    • Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures
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    • Choi, G.S.1    Iyer, R.K.2    Carreno, V.A.3
  • 10
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    • Baker, R.L.1    Mangum, L.S.2    Scheper, C.O.3
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    • A Measurement-Based Model for Workload Dependence of CPU Errors
    • No. June
    • R.K. Iyer and D.J. Rossetti, "A Measurement-Based Model for Workload Dependence of CPU Errors," IEEE Trans. Computers., vol. 35, No. pp. 511-519, June 1986.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.