Simulation based system level fault insertion using co-verification tools

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 704-710

  Eklow, Bill ^a   Hosseini, Anoosh ^a   Khuong, Chi ^a   Pullela, Shyam ^a   Vo, Toai ^a   Chau, Hien ^a  

^a CISCO SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN; CO-VERIFICATION; FAULT INSERTION; SYSTEM-ON-CHIP (SOC);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SOFTWARE ENGINEERING;

BUILT-IN SELF TEST;

EID: 18144369340     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. IEEE Standard Test Access Port and Boundary-Scan Architecture, 2001.
2. Savio Chau, "Fault Injection Boundary-Scan Design for Verification of Fault Tolerant Systems", International Test Conference, 1994.
3. th VLSI Test Symposium, 1994.
4. Phil Wilcox, Jim Hjartarson, Robert Hum, "Software Verification by Fault Insertion", U.S. Patent #5,130,988, 1992.
5. Benoit Nadeau-Dostie, Harry Hulvershorn, Saman M. I. Adnan, "A New Hardware Fault Insertion Scheme for System Diagnostics Verification", International Test Conference, 1995.
6. Cheryl Ajluni, "HW/SW Codesign and Coverification Come of Age, Electronic Design, June, 1992.