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Volumn , Issue , 2009, Pages

Tolerance of performance degrading faults for effective yield improvement

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTION; CLOCK FREQUENCY; CURRENT PRACTICES; FUNCTIONAL ERRORS; NANO-SCALE FABRICATION; PERFORMANCE DEGRADATION; POTENTIAL BENEFITS; STUCK-AT FAULTS; SYSTEM OUTPUT; SYSTEM PERFORMANCE DEGRADATION; USER PROGRAMS; YIELD IMPROVEMENT;

EID: 76549124009     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2009.5355594     Document Type: Conference Paper
Times cited : (24)

References (12)
  • 1
    • 3042622321 scopus 로고    scopus 로고
    • Defect and error-tolerance in the presence of massive numbers of defects
    • M. A. Breuer, S. K. Gupta, and T. M. Mak, "Defect and error-tolerance in the presence of massive numbers of defects," IEEE Design & Test of Computers 21(3): pages 216-227, 2004.
    • (2004) IEEE Design & Test of Computers , vol.21 , Issue.3 , pp. 216-227
    • Breuer, M.A.1    Gupta, S.K.2    Mak, T.M.3
  • 2
    • 42649096641 scopus 로고    scopus 로고
    • An illustrated methodology for analysis of error-tolerance
    • M. A. Breuer and H. Zhu, "An illustrated methodology for analysis of error-tolerance," IEEE Design & Test of Computers 25(2): pages 168-177, 2008.
    • (2008) IEEE Design & Test of Computers , vol.25 , Issue.2 , pp. 168-177
    • Breuer, M.A.1    Zhu, H.2
  • 4
  • 5
    • 13144266757 scopus 로고    scopus 로고
    • A process-tolerant cache architecture for improved yield in nanoscale technologies
    • A. Agarwal, B. C. Paul, H. Mahmoodi, A. Datta and K. Roy, "A process-tolerant cache architecture for improved yield in nanoscale technologies," IEEE Trans. on VLSI Systems, 13(1), pages 27-38, 2005.
    • (2005) IEEE Trans. on VLSI Systems , vol.13 , Issue.1 , pp. 27-38
    • Agarwal, A.1    Paul, B.C.2    Mahmoodi, H.3    Datta, A.4    Roy, K.5
  • 6
    • 0032639192 scopus 로고    scopus 로고
    • PADded cache: A new fault-tolerance technique for cache memories
    • P. P. Shirvani and E. J. McCluskey, "PADded cache: a new fault-tolerance technique for cache memories," VLSI Test Symp., pages 440-445, 1999.
    • (1999) VLSI Test Symp. , pp. 440-445
    • Shirvani, P.P.1    McCluskey, E.J.2
  • 7
    • 0345413275 scopus 로고    scopus 로고
    • Cost-effective graceful degradation in speculative processor subsystems: The branch prediction case
    • S. Almukhaizim, T. Verdel and Y. Markris, "Cost-effective graceful degradation in speculative processor subsystems: the branch prediction case," Int'l. Conf. on Computer Design, pages 194-197, 2003.
    • (2003) Int'l. Conf. on Computer Design , pp. 194-197
    • Almukhaizim, S.1    Verdel, T.2    Markris, Y.3
  • 9
    • 76549085735 scopus 로고    scopus 로고
    • Http://www.intel.com/technology/architecture-silicon/nextgen/whitepaper. pdf.
  • 10
    • 0012662716 scopus 로고
    • Combining branch predictors
    • Digital Equipment Corporation
    • S. McFarling, "Combining branch predictors," WRL Technical Note TN-36, Digital Equipment Corporation, 1993.
    • (1993) WRL Technical Note TN-36
    • McFarling, S.1
  • 11
    • 76549099136 scopus 로고    scopus 로고
    • SPEC2000 website
    • SPEC2000 website, www.spec.org/osg/cpu2000/.
  • 12
    • 0036469652 scopus 로고    scopus 로고
    • SimpleScalar: An infrastructure for computer system modeling
    • T. Austin, E. Larson and D. Ernst, "SimpleScalar: an infrastructure for computer system modeling," IEEE Computer, 35(2): pages 59-67, 2002.
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 59-67
    • Austin, T.1    Larson, E.2    Ernst, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.