Optimized BF3 P2 LAD implantation with Si-PAI for shallow, abrupt and high quality p+/n junctions formed using low temperature SPE annealing

Proceedings of the International Conference on Ion Implantation Technology

Volumn 22-27-September-2002, Issue , 2002, Pages 52-55

  Felch, Susan ^a   Borland, John ^a   Fang, Ziwei ^a   Koo, Bon Woong ^a   Gossmann, Hans ^b   Jones, Kevin ^c   Lindfors, Chad ^c  

^a VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

^b AGERE SYSTEMS   (United States)

^c UNIVERSITY OF FLORIDA   (United States)

Author keywords

Annealing; Diodes; Doping; Electrical resistance measurement; Epitaxial growth; High K dielectric materials; High K gate dielectrics; Plasma temperature; Silicon; Solids

Indexed keywords

ANNEALING; DIELECTRIC MATERIALS; DIODES; DOPING (ADDITIVES); EPITAXIAL GROWTH; GATE DIELECTRICS; HIGH-K DIELECTRIC; ION IMPLANTATION; OIL WELL FLOODING; RECONFIGURABLE HARDWARE; SILICON; SILICON WAFERS; SOLIDS; TRANSMISSION ELECTRON MICROSCOPY;

ACTIVATION TECHNIQUES; ELECTRICAL JUNCTIONS; ELECTRICAL RESISTANCE MEASUREMENT; HIGH- K GATE DIELECTRICS; JUNCTION LEAKAGE CURRENTS; PLASMA TEMPERATURE; SOLID PHASE EPITAXIAL GROWTH; SUB-100 NM TECHNOLOGIES;

TEMPERATURE;

EID: 76449095094     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIT.2002.1257936     Document Type: Conference Paper

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