Study of laser thermal processing (LTP) to meet sub 130 nm node shallow junction requirements

Proceedings of the International Conference on Ion Implantation Technology

Volumn , Issue , 2000, Pages 175-177

  Talwar, Somit ^a   Felch, Susan ^b   Downey, Dan ^b   Wang, Yun ^a  

^a Verdant Technologies   (United States)

^b VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

JUNCTION DEPTH; LASER THERMAL PROCESSING; LATERAL ABRUPTNESS; POSSIBLE SOLUTIONS; ROADMAP; SHALLOW JUNCTION; SOURCE-DRAIN EXTENSIONS;

ELECTRIC RESISTANCE; ION IMPLANTATION; LASER HEATING; RAPID THERMAL ANNEALING; SHEET RESISTANCE;

NANOTECHNOLOGY;

EID: 78649828329     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2000.924118     Document Type: Conference Paper

References (3)

1. S. Talwar, G. Verma, and K. Weiner, "Ultra-shallow, abrupt, and highly-activated junctions by low-energy ion implantation and laser annealing," 1998 International Conference on Ion Implantation Technology Proceedings, 1999, pp. 1 17 1 - 1 174.
2. Semiconductor Industry Association International Technology Roadmap for Semiconductors: 1999 Edition, Austin, TX: International SEMATECH, 1999.
3. S. Talwar, Yun Wang, Carol Gelatos, "Laser thermal Processing (LTP) for fabrication of ultra-shallow, hyper-abrupt, highly activated junctions for deca-nanometer MOS transistors," Electrochem. Soc. Symp. Proc., vol. 2000-9 (2000) pp. 95-106.