Mitigation of intra-array SRAM variability using adaptive voltage architecture

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 637-644

  Singh, Ashish K ^a   He, Ku ^a   Caramanis, Constantine ^a   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; COMPUTER AIDED DESIGN; CYTOLOGY; ENERGY EFFICIENCY; RANDOM PROCESSES; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

ADAPTIVE VOLTAGE; DESIGN STRATEGIES; EMPIRICAL DISTRIBUTIONS; ENERGY EFFICIENT; GUMBEL DISTRIBUTION; ORDER STATISTICS; READ ACCESS TIME; STATIC NOISE MARGIN;

INTEGRATED CIRCUIT DESIGN;

EID: 76349111804     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687517     Document Type: Conference Paper

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