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Volumn , Issue , 2009, Pages 531-538

Architecture-driven synthesis of reconfigurable cells

Author keywords

[No Author keywords available]

Indexed keywords

BENCH TESTS; COMPUTATIONAL PATTERNS; CONSTRAINT PROGRAMMING; CRITICAL PATHS; DESIGN CONSTRAINTS; NOVEL METHODS; RE-CONFIGURABLE; RUN-TIME RECONFIGURABLE; SPECIFIC DESIGN;

EID: 74549194552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.183     Document Type: Conference Paper
Times cited : (9)

References (13)
  • 2
    • 4444332421 scopus 로고    scopus 로고
    • Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
    • P. Brisk, A. Kaplan, and M. Sarrafzadeh. Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. Proc. 41st Design Automation Conference, pages 395-400, 2004.
    • (2004) Proc. 41st Design Automation Conference , pp. 395-400
    • Brisk, P.1    Kaplan, A.2    Sarrafzadeh, M.3
  • 3
    • 27444443319 scopus 로고    scopus 로고
    • Automated custom instruction generation for domain-specific processor acceleration
    • Oct
    • N. Clark, H. Zhong, and S. Mahlke. Automated custom instruction generation for domain-specific processor acceleration. IEEE Trans. Comput., 54(10):1258-1270, Oct. 2005.
    • (2005) IEEE Trans. Comput , vol.54 , Issue.10 , pp. 1258-1270
    • Clark, N.1    Zhong, H.2    Mahlke, S.3
  • 5
    • 0030211562 scopus 로고    scopus 로고
    • Performance optimization using template mapping for datapath-intensive high-level synthesis
    • Aug
    • M. Corazao, M. Khalaf, L. Guerra, M. Potkonjak, and J. Rabaey. Performance optimization using template mapping for datapath-intensive high-level synthesis. IEEE Trans. Computer-Aided Design, 15(8):877-888, Aug. 2004.
    • (2004) IEEE Trans. Computer-Aided Design , vol.15 , Issue.8 , pp. 877-888
    • Corazao, M.1    Khalaf, M.2    Guerra, L.3    Potkonjak, M.4    Rabaey, J.5
  • 9
    • 22544461314 scopus 로고    scopus 로고
    • Efficient datapath merging for partially reconfigurable architectures
    • July
    • N. Moreano, E. Borin, C. de Souza, and G. Araujo. Efficient datapath merging for partially reconfigurable architectures. IEEE Trans. Computer-Aided Design, 24(7):969-980, July 2005.
    • (2005) IEEE Trans. Computer-Aided Design , vol.24 , Issue.7 , pp. 969-980
    • Moreano, N.1    Borin, E.2    de Souza, C.3    Araujo, G.4
  • 10
    • 74549212214 scopus 로고    scopus 로고
    • Solving the maximum clique problem with constraint programming
    • J.-C. Régin. Solving the maximum clique problem with constraint programming. In Proc. CPAIOR, 2003.
    • (2003) Proc. CPAIOR
    • Régin, J.-C.1
  • 11
    • 49749147599 scopus 로고    scopus 로고
    • Computation patterns identification for instruction set extensions implemented as reconfigurable hardware
    • Las Vegas, Nevada, USA, June 25-28
    • C. Wolinski and K. Kuchcinski. Computation patterns identification for instruction set extensions implemented as reconfigurable hardware. In The Int. Conf. on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, June 25-28, 2007.
    • (2007) The Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    • Wolinski, C.1    Kuchcinski, K.2
  • 13
    • 49749153429 scopus 로고    scopus 로고
    • Automatic selection of application-specific reconfigurable processor extensions
    • Munich, Germany, Mar. 10-14
    • C. Wolinski and K. Kuchcinski. Automatic selection of application-specific reconfigurable processor extensions. In Proc. Design Automation and Test in Europe, Munich, Germany, Mar. 10-14, 2008.
    • (2008) Proc. Design Automation and Test in Europe
    • Wolinski, C.1    Kuchcinski, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.