The CHIP - A design guide for reducing substrate noise coupling in RF applications

IEEE Circuits and Devices Magazine

Volumn 22, Issue 5, 2006, Pages 7-21

  Helmy, Ahmed ^a   Ismail, Mohammed ^b  

^a Ohio State University   (United States)

^b OHIO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTEGRATED CIRCUITS; OPTIMIZATION; SILICON WAFERS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

BASELINE ISOLATION TECHNIQUES; SUBMICRON TECHNOLOGIES; SUBSTRATE NOISE COUPLING;

MICROPROCESSOR CHIPS;

EID: 33846097203     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2006.272996     Document Type: Article

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