Pulse generation for on-chip data transmission

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 303-310

  Hollis, Simon J ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

1 GBIT/S; ASYNCHRONOUS NETWORKS; DATA RATES; DATA TRANSMISSION; INPUT SIGNAL; LOW LATENCY; ON CHIPS; POWER-SAVING; PULSE GENERATION; RLC MODEL; SIGNAL INTEGRITY; WIRE LENGTH;

COMPUTER SIMULATION; DESIGN; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; SIGNAL GENERATORS; WIRE;

PULSE GENERATORS;

EID: 74549159620     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.176     Document Type: Conference Paper

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