Parameterizing simulated annealing for distributing Kahn process networks on multiprocessor SoCs

2009 International Symposium on System-on-Chip - Proceedings, SoC 2009

Volumn , Issue , 2009, Pages 19-26

  Orsila, Heikki ^a   Salminen, Erno ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ACYCLIC GRAPHS; APPLICATION EXECUTION; ARCHITECTURE EXPLORATION; BRUTE FORCE; BRUTE FORCE ALGORITHMS; CYCLIC GRAPH; GLOBAL OPTIMUM; GLOBAL OPTIMUM SOLUTIONS; GROUP MIGRATION; KAHN PROCESS NETWORKS; MULTIPROCESSOR SYSTEM ON CHIPS; OPTIMIZATION PROBLEMS; PARAMETER SELECTION; PARAMETERIZING; RANDOM MAPPINGS; TASK DISTRIBUTION; TRANSITION PROBABILITIES;

ANNEALING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; MAPPING; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SENSITIVITY ANALYSIS; THREE TERM CONTROL SYSTEMS;

SIMULATED ANNEALING;

EID: 74549113696     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2009.5335683     Document Type: Conference Paper

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