Mapping and scheduling for architecture exploration of networking SoCs

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 376-381

  Wild, T ^a   Foag, J ^a   Pazos, N ^a   Brunnbauer, W ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES   (United States)

Author keywords

Constraint optimization; Context; Delay; NP complete problem; Parallel processing; Partitioning algorithms; Polynomials; Proposals; Scheduling; Very large scale integration

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINED OPTIMIZATION; DATA TRANSFER; DESIGN; EMBEDDED SOFTWARE; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; POLYNOMIALS; PROBLEM SOLVING; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING; SIMULATED ANNEALING; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; TABU SEARCH; VLSI CIRCUITS;

CONSTRAINT OPTIMIZATIONS; CONTEXT; DELAY; PARALLEL PROCESSING; PARTITIONING ALGORITHMS; PROPOSALS;

EMBEDDED SYSTEMS;

EID: 84941330141     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183165     Document Type: Conference Paper

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