32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

Microelectronic Engineering

Volumn 87, Issue 3, 2010, Pages 316-320

  Hamioud, K ^a,c   Arnal, V ^a   Farcy, A ^a   Jousseaume, V ^b   Zenasni, A ^b   Icard, B ^b   Pradelles, J ^b   Manakli, S ^a   Brun, Ph ^b   Imbert, G ^a   Jayet, C ^b   Assous, M ^b   Maitrejean, S ^b   Galpin, D ^a   Monget, C ^a   Guillan, J ^a   Chhun, S ^a   Richard, E ^a   Barbier, D ^c   Haond, M ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

^c INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

32 nm; BEOL architecture; Extreme low k k = 2.3; Integration; Porous SiOCH; RC product

Indexed keywords

32 NM; 32-NM NODE; BEOL ARCHITECTURE; BEOL INTEGRATION; DUAL DAMASCENE ARCHITECTURE; INTERMEDIATE LEVEL; LINE RESISTANCE; METALLIZATIONS; MULTI-LEVEL; PERFORMANCE SPECIFICATIONS; TEST VEHICLE; TRENCH FIRST HARD MASKS; VIA CHAIN;

NANOTECHNOLOGY;

DIELECTRIC MATERIALS;

EID: 74449092466     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.07.008     Document Type: Article

References (9)

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