Manufacturability and speed performance demonstration of porous ULK (k=2.5) for a 45nm CMOS platform

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 178-179

  Richard, E ^a   Fox, R ^b   Monget, C ^c   Zaleski, M ^b   Ferreira, P ^c   Guvenilir, A ^b   Brun, P ^d   Ollier, E ^a   Guillermet, M ^d   Mellier, M ^a   Petitdidier, S ^c   Delsol, R ^a   Besling, W ^a   Marinier, L ^a   Imbert, G ^c   Lagha, A ^b   Broussous, L ^c   Rasco, M ^b   Cregut, C ^c   Downey, S ^b   Huang, G ^a   Haond, M ^c   Cave, N ^b   Perera, A ^b   more..

^a NXP SEMICONDUCTORS   (France)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c STMICROELECTRONICS   (France)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; METALS; MICROPROCESSOR CHIPS; SPEED;

193 NM IMMERSION; 65NM TECHNOLOGY; HARD MASKS; HIGH-DENSITY; HYPER-NA; LOW K DIELECTRICS; MANUFACTURABILITY; METAL FEATURES; MICROPROCESSOR APPLICATIONS; NUMERICAL APERTURE (NA); OPTICAL PROXIMITY CORRECTION (OPC); POROUS ULK; SPEED PERFORMANCE; ULTRA LOW K (ULK); VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 47249125724     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339683     Document Type: Conference Paper

References (5)

1. O. Hinsinger et al., IEDM Technical Digest, pp. 317-320, 2004.
2. R.Fox et al., IEDM 2005 Technical Digest, pp. 87-90
3. M.-S. Liang et al, IEDM Technical Digest, pp. 313-316, 2004.
4. S. Kondo et al, Symposium on VLSI Technology., p. 68-9 (2004)
5. W.F.A Besling et al. IEDM 2004 Technical Digest, p. 325