Bottom-up copper electroplating using transfer wafers for fabrication of high aspect-ratio through-silicon-vias

Microelectronic Engineering

Volumn 87, Issue 3, 2010, Pages 510-513

  Song, Chongshen ^a   Wang, Zheyao ^a   Liu, Litian ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

3D integration; Bottom up copper electroplating (BCE); Through silicon vias (TSVs); Transfer wafer

Indexed keywords

3-D INTEGRATION; COPPER ELECTROPLATING; COPPER SEED; DEVICE WAFERS; HIGH ASPECT RATIO; MECHANICAL SUPPORT; MOORE'S LAW; SEALING PROCESS; SEED LAYER; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH HOLE; THROUGH SILICON VIAS; TRANSFER WAFER;

ASPECT RATIO; COPPER; COPPER PLATING; ELECTROPLATING; SEMICONDUCTING SILICON COMPOUNDS; THREE DIMENSIONAL; WAFER BONDING;

SILICON WAFERS;

EID: 74449088887     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.06.029     Document Type: Article

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