-
1
-
-
84904295483
-
-
Internet Routing Table Statistics, May
-
Internet Routing Table Statistics, "http://www.merit.edu/ipmalouting_table/, May 2001".
-
(2001)
-
-
-
2
-
-
0003254657
-
Classless inter-domain routing (CIDR): An address and aggregation strategy
-
September
-
S. Fuler, T. Li, and K. Varadhan, "Classless inter-domain routing (CIDR): An address and aggregation strategy", RFC 1519, September 1993.
-
(1993)
RFC
, pp. 1519
-
-
Fuler, S.1
Li, T.2
Varadhan, K.3
-
3
-
-
0031679714
-
Routing Tables in hardware at memory access speeds
-
Pankaj Gupta. Steven Lin, and Nick McKeownm "Routing Tables in hardware at memory access speeds", in IEEE Infocom, 1998.
-
(1998)
IEEE Infocom
-
-
Gupta, P.1
Lin, S.2
McKeownm, N.3
-
5
-
-
0004755523
-
Faster IP lookups using controlled prefix expansion
-
V. Srinivisan and V. Varghese, "Faster IP lookups using controlled prefix expansion", in SIGMETRICS, 1998.
-
(1998)
SIGMETRICS
-
-
Srinivisan, V.1
Varghese, V.2
-
7
-
-
84904294322
-
SiberCAM Ultra-2M SCT200
-
SiberCode Technologies Inc
-
SiberCode Technologies Inc., "SiberCAM Ultra-2M SCT200", Product Brief, 2000.
-
(2000)
Product Brief
-
-
-
8
-
-
0030609298
-
Scalable high speed IP routing table lookups
-
Marcel Waldvogel, Georges Varghese, John Turner, and Bernhardd Plattner, "Scalable high speed IP routing table lookups", in Proc. Of ACM SIGCOMM'97, pp. 25-36.
-
Proc. of ACM SIGCOMM'97
, pp. 25-36
-
-
Waldvogel, M.1
Varghese, G.2
Turner, J.3
Plattner, B.4
-
9
-
-
84883897331
-
Method for compiling high level programs into hardware
-
JSP2000-313818
-
M. Meribout and M. Motomura, "Method for compiling high level programs into hardware", Japanese Patent: JSP2000-313818, 2000.
-
(2000)
Japanese Patent:
-
-
Meribout, M.1
Motomura, M.2
-
11
-
-
84904359432
-
The Viretex user data sheet
-
"The Viretex user data sheet", Xilinx, 2001.
-
(2001)
Xilinx
-
-
-
12
-
-
0031360875
-
An Embedded DRAM-FPGA Chip with Instantaneous Logic reconfiguration
-
July
-
M. Motomura et al, "An Embedded DRAM-FPGA Chip with Instantaneous Logic reconfiguration", Symposium on VLSI Circuits, pp. 55-56, July 1997.
-
(1997)
Symposium On VLSI Circuits
, pp. 55-56
-
-
Motomura, M.1
-
15
-
-
0037370416
-
New Design Methodology with Efficient Prediction of Quality Metrics for Logic Level Design Towards Dynamic Reconfigurable Logic
-
(Elsevier Science Ltd)
-
M. Meribout and M. Motomura, New Design Methodology with Efficient Prediction of Quality Metrics for Logic Level Design Towards Dynamic Reconfigurable Logic, International Journal for Systems Architecture (JSA), (Elsevier Science Ltd), vol. 48/8-10, pp. 285-310, 2003.
-
(2003)
International Journal For Systems Architecture (JSA)
, vol.48
, Issue.8-10
, pp. 285-310
-
-
Meribout, M.1
Motomura, M.2
-
16
-
-
84962194782
-
Dynamic Hardware Plugins (DHP): Exploiting reconfigurable hardware for high performance programmable routers
-
Anchorage, AK, April
-
David E. Taylor, Jon Tunner, and John W. Loclwood, "Dynamic Hardware Plugins (DHP): Exploiting reconfigurable hardware for high performance programmable routers," In IEEE OPENARCH 2001, Anchorage, AK, April, 2001.
-
(2001)
IEEE OPENARCH 2001
-
-
Taylor, D.E.1
Tunner, J.2
Loclwood, J.W.3
-
17
-
-
84904354990
-
-
ns notes and documentation, UC Berkeley, LBL, USC/ISI, and Xerox PARC, November, Available from
-
ns notes and documentation. The VINT Project, UC Berkeley, LBL, USC/ISI, and Xerox PARC, November 1997. Available from http://www-mash.cs.berkeley.edu/ns/.
-
(1997)
The VINT Project
-
-
-
18
-
-
84904339280
-
-
URL
-
URL: www.Mentorgraphics.com.
-
-
-
|