Energy optimization in a network-on-chip with dynamically reconfigurable processing nodes

Proceedings of the IEEE International Conference on Control Applications

Volumn , Issue , 2009, Pages 308-313

  Nunez Yanez, J L ^a   Hosseinabady, M ^a   Nabina, A ^a   Zaidi, I ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC; AVAILABLE ENERGY; CONTROL ALGORITHMS; DYNAMIC NATURE; DYNAMIC RE-CONFIGURATION; ENERGY OPTIMIZATION; FREQUENCY-SCALING; NETWORK ON CHIP; OPERATING SYSTEMS; PROCESSING NODES; PROCESSING PERFORMANCE; RECONFIGURABLE FABRICS; RECONFIGURABLE PROCESSING; VIRTUAL PROCESSOR;

ALGORITHMS; COMPUTER OPERATING SYSTEMS; DISTRIBUTED PARAMETER CONTROL SYSTEMS; DYNAMIC MODELS; ELECTRIC NETWORK TOPOLOGY; FABRICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

RECONFIGURABLE HARDWARE;

EID: 74049085514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCA.2009.5281128     Document Type: Conference Paper

References (8)

1. Information available at http://public.itrs.net/
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3. D. Bursky, "We must hold the line on soaring ASIC design costs", Electornic Design, www.elecdesign.com, October, 2002.
4. S. Kumar, et al., "A Network on Chip Architecture and Design Methodology," IEEE Annual Symposium on VLSI, ISVLSI'02.
5. L. Benini and G. De Micheli. "Networks on chips: A new SoC paradigm," IEEE Computer, 35(1):70-80, 2002
6. J. Dielissen, et al. "Concepts and implementation of the philips network-on-chip," D&R Industry, www.design-reuse.com
7. D. Bertozzi, et al., "Xpipes: A network-on-chip architecture for gigascale systems-on-chip," IEEE circuit and systems, 4(2):18-31,2004
8. J.L. Nunez-Yanez, et al., "A configurable and programmable motion estimation processor for the H.264 video codec," (FPL'08), pp.149-154, Sept. 2008.