System level speedup oriented cache partitioning for multi-programmed systems

NPC 2009 - 6th International Conference on Network and Parallel Computing

Volumn , Issue , 2009, Pages 204-210

  Suo, Guang ^a   Yang, Xue Jun ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE PARTITIONING; CHIP-MULTIPROCESSOR; CURRENT PERFORMANCE; INSTRUCTION PER CYCLES; MISS-RATE; MULTIPLE APPLICATIONS; SHARED CACHE; SYSTEM LEVELS; TOTAL SPEEDUPS;

MULTIPROGRAMMING;

PARALLEL ARCHITECTURES;

EID: 73449088742     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NPC.2009.9     Document Type: Conference Paper

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