A single-40 Gb/s dual-20 Gb/s serializer IC with SFI-5.2 interface in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 12, 2009, Pages 3580-3589

  Kanda, Kouichi ^a   Tamura, Hirotaka ^a   Yamamoto, Takuji ^a   Matsubara, Satoshi ^a   Kibune, Masaya ^a   Doi, Yoshiyasu ^a   Shibasaki, Takayuki ^a   Tzartzanis, Nestoras ^b   Kristensson, Anders ^b   Parikh, Samir ^b   Ide, Satoshi ^a   Tsunoda, Yukito ^a   Yamabana, Tetsuji ^a   Sugawara, Mariko ^a   Kuwata, Naoki ^a   Ikeuchi, Tadashi ^a   Ogawa, Junji ^a   Walker, William W ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

40 Gb s; 65 nm CMOS; DQPSK; OC 768; SFI5.2

Indexed keywords

10 GB/ S; 20 GB/S; 40 GB/S; BULK CMOS; ERROR FREE OPERATIONS; G-MODES; INPUT INTERFACE; POWER SUPPLY; SERIALIZERS;

CMOS INTEGRATED CIRCUITS; POLYCHLORINATED BIPHENYLS;

QUADRATURE PHASE SHIFT KEYING;

EID: 72949095497     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2031030     Document Type: Conference Paper

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