The SiGe heterojunction source PNPN n-MOSFET with SSOI for low power application

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2009, Pages

  Chang, Hsu Yu ^a   Venkatagirish, N ^a   Tura, Ahmet ^a   Jhaveri, Ritesh ^a   Woo, Jason ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BAND TO BAND TUNNELING; LOW POWER APPLICATION; NMOSFET; NOVEL DEVICES; ON CURRENTS; SI-GE HETEROJUNCTION; SUBTHRESHOLD SWING; TUNNEL FET; TUNNELING FET;

FIELD EFFECT TRANSISTORS; HETEROJUNCTIONS; MESFET DEVICES; MOSFET DEVICES; SEMICONDUCTING GERMANIUM COMPOUNDS; SILICON ALLOYS; TUNNELING (EXCAVATION); TUNNELS; WIND TUNNELS;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 72449183253     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2009.5318740     Document Type: Conference Paper

References (5)

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2. F. Mayer, C. Le Royer, J. F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali and S. Deleonibus, "Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance," IEDM, pp. 163-166, 2008.
3. V. Nagavarapu, R. Jhaveri and J. C. S. Woo, "The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor," IEEE Trans. On Electron Devices, Vol. 55, pp. 1013-1019, 2008
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5. R. M. Huang, Y. H. Lin, S. H. Tsai, C. W. Yang, E. C. Liu, Y. S. Hsieh, I. Cayrefourcq, C. T. Tsai and G. H. Ma, "Thermal budget optimization on Strained Silicon-On-Insulator (SSOI) CMOS," VLSI-TSA, pp.118-119, 2008