Reliability modeling of MEMS devices on CUDA based HPC setup

1st South Central Asian Himalayas Regional IEEE/IFIP International Conference on Internet, AH-ICI 2009

Volumn , Issue , 2009, Pages

  Pathak, Rohit ^a   Joshi, Satyadhar ^b  

^a ACROPOLIS INSTITUTE OF TECHNOLOGY AND RESEARCH   (India)

^b SHRI VAISHNAV INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER SYNCHRONIZATION; C LANGUAGE; COARSE-GRAINED; DATA PARALLELISM; FAILURE RATE FUNCTIONS; HIGH-PERFORMANCE COMPUTING; MEAN TIME TO FAILURE; MEMS TECHNOLOGY; MEMSDEVICES; PHYSICAL PROCESSORS; PROCESSOR CORES; RELIABILITY CALCULATION; RELIABILITY FUNCTIONS; RELIABILITY MODELING; RESIDUAL TIME; RUNTIME SYSTEMS; SHARED MEMORIES; SUB-PROBLEMS; TASK PARALLELISM; THREAD GROUPS;

FLUORINE CONTAINING POLYMERS; INTERNET; LINGUISTICS; MEMS; MICROELECTROMECHANICAL DEVICES; QUALITY ASSURANCE;

RELIABILITY ANALYSIS;

EID: 71849117629     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/AHICI.2009.5340289     Document Type: Conference Paper

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