A compiler framework for optimization of affine loop nests for GPGPUs

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2008, Pages 225-234

  Baskaran, Muthu Manikandan ^a   Bondhugula, Uday ^a   Krishnamoorthy, Sriram ^a   Ramanujam, J ^b   Rountev, Atanas ^a   Sadayappan, P ^a  

^a The Ohio State University

^b Louisiana State University

Author keywords

Empirical tuning; GPU; Memory access optimization; Polyhedral model

Indexed keywords

AUTOMATIC PARALLELIZATION; COMPILER OPTIMIZATIONS; COMPUTATIONAL POWERS; DATA ACCESSES; DATA DEPENDENCES; DEVICE ARCHITECTURES; EMPIRICAL TUNING; GPU; LOOP NESTS; MEMORY ACCESS OPTIMIZATION; OPTIMAL PARAMETERS; PARALLEL ARCHITECTURES; PARALLEL CODES; PERFORMANCE OPTIMIZATIONS; POLYHEDRAL MODEL; PROGRAM TRANSFORMATIONS; PROGRAMMING MODELS; SHARED MEMORIES;

COMPUTERS; INTELLIGENT CONTROL; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; PROGRAM COMPILERS; PROGRAM PROCESSORS; STRUCTURED PROGRAMMING; SYSTEMS ANALYSIS;

GLOBAL OPTIMIZATION;

EID: 57349180412     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1375527.1375562     Document Type: Conference Paper

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