Study on fine-grained synchronization in many-core architecture

10th ACIS Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2009, In conjunction with IWEA 2009 and WEACR 2009

Volumn , Issue , 2009, Pages 524-529

  Yu, Lei ^a,b   Liu, Zhiyong ^a   Fan, Dongrui ^a   Song, Fenglong ^a,b   Zhang, Junchao ^a   Yuan, Nan ^a,b  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

Author keywords

Fine grained synchronization; Many core; Speedup; Thread level parallelism

Indexed keywords

COARSE-GRAINED; DATA ALLOCATION; EFFICIENT METHOD; EXECUTION TIME; GLOBAL BARRIERS; GODSON-T; LU DECOMPOSITION; MANY-CORE; MANY-CORE ARCHITECTURE; MEMORY ACCESS; ON-CHIP STORAGE; PERFORMANCE IMPROVEMENTS; SCIENTIFIC COMPUTATION; SPEEDUP; SYNCHRONIZATION ALGORITHM; THREAD LEVEL PARALLELISM;

ARTIFICIAL INTELLIGENCE; COMPUTATION THEORY; COMPUTATIONAL EFFICIENCY; COMPUTATIONAL FLUID DYNAMICS; COMPUTER SOFTWARE; EXPERIMENTS;

SYNCHRONIZATION;

EID: 71249109835     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SNPD.2009.61     Document Type: Conference Paper

References (16)

1. K. Asanovic, R. Bodik, B. C. Catanzaro, "The Landscape of Parallel Computing Research: A View from Berkeley" www.eecs.berkeley.edu/Pubs/ TechRpts/2006/EECS-2006-183.html
2. J. Sampson, R. Gonzalez, J.-F. Collard, N. Jouppi, M. Schlansker, and B. Calder. "Exploiting fine-grained data parallelism with chip multiprocessors and fast barriers". In Procs. of the Intl. Symp. on Microarchitecture, Page(s):235 - 246 ,micro 2006 .
3. D.M Tullsen,. Lo, J.L., S.J Eggers,. Levy, H.M. "Supporting fine-grained synchronization on a simultaneous multithreading processor", International Symposium On High-Performance Computer Architecture, 1999. Proceedings page(s): 54-58 Orlando, FL, USA
4. W.R Zhu, C.Vugranam, Sreedhar, Z.Hu, G. R. Gao ,Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization on Many-Core Architectures.In proceedings of the 34th international symposium computer architecture (ISCA 2007),San Diego,USA,June pages 35-45
5. S. C. Woo, M. Ohara, E. Torrie, J. Pal Singh, and A. Gupta. "The SPLASH-2 Programs: Characterization and Methodological Considerations". In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24-36, Santa Margherita Ligure, Italy, June 1995.
6. W. Lin, X.C Ye, F.L. Song et al. "Using write mask to support hybrid write-back and write-through cache policy on Many-core architectures", Chinese Journal of Computers, Vol 32, No.11 , 1918-1927, Nov. 2008
7. I. E. Venetis and G. R. Gao. "Optimizing the LU Benchmark for the Cyclops-64 Architecture". CAPSL Technical Memo 75, University of Delaware, Feb. 2007.
8. S. Vangal, J. Howard, G. Ruhl, and et. al. "An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS".pages 98-589, In Procs. Of 2007 Intl. Solid-State Circuits Conf., Feb. 2007.
9. J. Cuvillo, W. Zhu, Z. Hu, and G. R. Gao. "Fast: Afunctionally accurate simulation toolset for the cyclops-64 cellular architecture". In Workshop on Modeling, Benchmarking and Simulation (MoBS), pages 11-20,Madison ,Wisconsin, June ,2005.
10. G.M Tan, N.H Sun, G R. Gao. "A Parallel Dynamic Programming Algorithm on a Multi-core Architecture" SPAA'07, pages 465-476,June 9-11, 2007, San Diego, California, USA.
11. G.B Hong. "Fine-Grain in Parallelism and Multi-Thread Computing, Computer Research and Development", Chinese Journal, Vo l. 33 No. 6, June 1996, 473-476
12. S.Kumar ,C. J. Hughes, A. Nguyen, "Carbon: Architectural Support for Fine-Grained Parallelism on Chip Multiprocessors", ISCA'07, June 9-13, 2007, San Diego, California, USA.pages 162-173
13. Michael Chu, Rajiv Ravindrany, Scott Mahlke, "Data Access Partitioning for Fine grain Parallelism on Multicore Architectures", page(s): 369-380, The 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007 MICRO 2007, December, 1--5 2007,Chicago, Illinois, USA
14. M. Herlihy. "A methodology for implementing highly concurrent data objects". In Symposium on Principles and Practices of Parallel Programming, March 1990. Pages: 45 - 46
15. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porter, and B. Smith. "The Tera computer system". In International Conference on Supercomputing, June 1990. pages 1-6
16. M. Herlihy and J. E. B. Moss. "Transactional memory: architectural support for lock-free data structures". In Procs. of the 20th Intl. Symp. on Computer architecture, 1993. pages 289-300