Incremental physical resynthesis for timing optimization

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn 12, Issue , 2004, Pages 99-108

  Suaris, Peter ^a   Liu, Lungtien ^a   Ding, Yuzheng ^a   Chou, Nanchi ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

FPGA; Logic synthesis; Placement; Timing Optimization

Indexed keywords

AUTOMATION; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; PERFORMANCE; RESOURCE ALLOCATION;

LOGIC RESTRUCTURING; LOGIC SYNTHESIS; PLACEMENT; SIGNAL ROUTING; TIMING OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2442466856     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968296     Document Type: Conference Paper

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