Through-silicon via fill for 3D interconnect applications

ECS Transactions

Volumn 16, Issue 22, 2009, Pages 33-40

  Mathew, V ^a   Chatterjee, R ^a   Jones, R ^a   Garcia, S ^a   Acosta, E ^a   Huang, Z ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D INTERCONNECT; BATH COMPOSITIONS; COPPER SEED; ELECTRICAL CONTINUITY; ELECTROLESS; HIGH ASPECT RATIO; HIGH DENSITY; MULTI-CHIP; PLATING CONDITIONS; PLATING PROCESS; POWER CONSUMPTION; PROCESS STEPS; SEED ENHANCEMENT; SIGNAL DELAYS; THROUGH SILICON VIAS; VIA FILL; VOID-FREE;

ASPECT RATIO; DEPOSITION; SEED; TITANIUM NITRIDE;

ELECTRONICS PACKAGING;

EID: 70449646807     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3115648     Document Type: Conference Paper

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