A mixed-mode analog neural network using current-steering synapses

Analog Integrated Circuits and Signal Processing

Volumn 38, Issue 2-3, 2004, Pages 233-244

  Schemmel, Johannes ^a   Hohmann, Steffen ^a   Meier, Karlheinz ^a   Schürmann, Felix ^a  

^a UNIVERSITY OF HEIDELBERG   (Germany)

Author keywords

Analog computing; Current mode; Massively parallel; Neural network

Indexed keywords

DIGITAL TO ANALOG CONVERSION; FIELD PROGRAMMABLE GATE ARRAYS; LINEAR INTEGRATED CIRCUITS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; MULTILAYER NEURAL NETWORKS; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

ANALOG COMPUTING; CURRENT MODE CIRCUITS; CURRENT STEERING SYNAPSES; MASSIVELY PARALLEL; MIXED MODE ANALOG NEURAL NETWORK;

CMOS INTEGRATED CIRCUITS;

EID: 1442313963     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/b:alog.0000011170.92377.6e     Document Type: Article

References (10)

1. S. Satyanarayana, P. Tsividis, and H.P. Graf, "A reconfigurable VLSI neural network." IEEE Journal of Solid-State Circuits, vol. 27, no. 1, pp. 67-81, 1992.
2. F. Diotalevi, M. Valle, G.M. Bao, and D.D. Caviglia, "A VLSI architecture for weight perturbation on chip learning implementation," in Proceedings IJCNN 2000, IEEE, 2000, vol. 4, pp. 219-224.
3. J. Schemmel, S. Hohmann, F. Schürmann, and K. Meier, "An integrated mixed-mode neural network architecture for megasynapse ANNs," in Proceedings IJCNN 2000, IEEE, ISBN 0-7803-7278-6, 2002, pp. 2704-2710.
4. B. Boser et al., "An analog neural network processor with programmable topology." IEEE Journal of Solid-State Circuits, vol. 26, no. 12, pp. 2017-2025, 1991.
5. A. Kramer, "Array-based analog computation." IEEE Micro, pp. 20-29, Oct. 1996.
6. ANSI/TIA/EIA-644 1995 Telecommunications Industry Association, Electrical Characteristics of Low Voltage Differential Signaling (LVDS), March 1996.
7. P. Allen and D. Holberg, CMOS Analog Circuit Design. Oxford University Press, ISBN 0-19-511644-5, 2002, pp. 483-488.
8. J. Pujol and R. Poli, "Evolving neural networks using a dual representation with a combined crossover operator," in Proceedings of the IEEE International Conference on Evolutionary Computation (ICEC), pp. 416-421, 1998.
9. J. Montalvo, R. Gyurcsik, and J. Paulos, "An analog VLSI neural network with on-chip perturbation learning." IEEE Journal of Solid-State Circuits, vol. 32, no. 4, pp. 535-543, 1997.
10. J. Schemmel, K. Meier, and F. Schürmann, "A VLSI implementation of an analog neural network suited for genetic algorithms," in Proceedings ICES 2001, Springer, ISBN 3-540-42671-X, 2001, pp. 50-61.