Design and test challenges in resistive switching ram (reram): An electrical model for defect injections

Proceedings of the 14th IEEE European Test Symposium, ETS 2009

Volumn , Issue , 2009, Pages 61-66

  Ginez, O ^a   Portal, J M ^a   Muller, Ch ^a  

^a AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

Defect Injection; Electrical Simulation; Memory Testing; ReRAM

Indexed keywords

CHARGE STORAGE; CMOS PROCESSS; DEFECT INJECTION; DEFECT INJECTIONS; ELECTRICAL MODELS; ELECTRICAL SIMULATION; MATERIAL PHYSICS; MEMORY CIRCUITS; MEMORY ELEMENT; MEMORY TESTING; NON-VOLATILE MEMORIES; RERAM; RESISTIVE STATE; RESISTIVE SWITCHING; RESISTIVE SWITCHING MEMORIES; ROBUSTNESS ASSESSMENT; SWITCHING MECHANISM;

DEFECTS; DESIGN; ELECTRIC LOAD FORECASTING; SIMULATORS; SWITCHING SYSTEMS;

TESTING;

EID: 70449339550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2009.23     Document Type: Conference Paper

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