Spatial and temporal design debug using partial maxsat

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2009, Pages 345-350

  Chen, Yibin ^a   Safarpou, Sean ^a   Veneris, Andreas ^a   Marques Silva, Joao ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

Design Debugging; Maximum Satisfiability

Indexed keywords

AUTOMATED SOLUTIONS; DEBUG TECHNIQUES; DEBUGGING PROCESS; DESIGN DEBUG; ERROR SOURCES; MAX-SAT; MAXIMUM SATISFIABILITY; ORDERS OF MAGNITUDE; PERFORMANCE IMPROVEMENTS; RUNTIMES; SIMULATION TIME; TEMPORAL INFORMATION; VLSI DESIGN;

EMBEDDED SYSTEMS; LAKES; SIMULATORS;

DESIGN;

EID: 70350605269     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531542.1531621     Document Type: Conference Paper

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