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Volumn , Issue , 2004, Pages 139-147

A fading algorithm for sequential fault diagnosis

Author keywords

[No Author keywords available]

Indexed keywords

BASELINE ENHANCEMENT; FADING ALGORITHM; FADING SCHEMES; FAULT EFFECT;

EID: 24944468877     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2004.1347834     Document Type: Conference Paper
Times cited : (8)

References (9)
  • 4
    • 0022769976 scopus 로고
    • Graph-based algorithms for boolean function manipulation
    • Aug.
    • R. E. Bryant, "Graph-based Algorithms for Boolean Function Manipulation", IEEE Trans. on Computers, vol. 35, No. 8, pp. 677-691, (Aug. 1986).
    • (1986) IEEE Trans. on Computers , vol.35 , Issue.8 , pp. 677-691
    • Bryant, R.E.1
  • 5
    • 0032595832 scopus 로고    scopus 로고
    • ErrorTracer: A fault simulation based approach to design error diagnosis
    • Sept.
    • S.-Y. Huang and K.-T. Cheng, "ErrorTracer: A Fault Simulation Based Approach to Design Error Diagnosis," IEEE Trans. on Computer-Aided Design, pp. 1341-1352, (Sept. 1999).
    • (1999) IEEE Trans. on Computer-aided Design , pp. 1341-1352
    • Huang, S.-Y.1    Cheng, K.-T.2
  • 6
    • 0037379321 scopus 로고    scopus 로고
    • A symbolic inject-and-evaluate paradigm for byzantine fault diagnosis
    • April
    • S.-Y. Huang, "A Symbolic Inject-And-Evaluate Paradigm For Byzantine Fault Diagnosis," Journal of Electronic Testing, Theory and Application (JETTA), Vol. 19, No. 2, pp. 161-172, (April 2003).
    • (2003) Journal of Electronic Testing, Theory and Application (JETTA) , vol.19 , Issue.2 , pp. 161-172
    • Huang, S.-Y.1
  • 7
    • 0030383964 scopus 로고    scopus 로고
    • Beyond the byzantine generals: Unexpected behavior and bridging fault diagnosis
    • D. B. Lavo, T. Larabee, and B. Chess, "Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis," Proc. of Int'l Test Conference, pp. 611-619, (1996).
    • (1996) Proc. of Int'l Test Conference , pp. 611-619
    • Lavo, D.B.1    Larabee, T.2    Chess, B.3
  • 8
    • 24944476413 scopus 로고    scopus 로고
    • Chip-level strategy for full-scan designs with multiple faults
    • Nov.
    • Y.-C. Lin and S.-Y. Huang, "Chip-Level Strategy For Full-Scan Designs With Multiple Faults," Proc. of Asian Test Symposium, pp. 38-44, (Nov. 2003).
    • (2003) Proc. of Asian Test Symposium , pp. 38-44
    • Lin, Y.-C.1    Huang, S.-Y.2
  • 9
    • 0033743138 scopus 로고    scopus 로고
    • A technique for logic fault diagnosis of interconnect open faults
    • S. Venkataraman, S. B. Drummonds, "A Technique for Logic Fault Diagnosis of Interconnect Open Faults," Proc. of VLSI Test Symposium, pp.313-318, (2000).
    • (2000) Proc. of VLSI Test Symposium , pp. 313-318
    • Venkataraman, S.1    Drummonds, S.B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.