Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009

Volumn , Issue , 2009, Pages 80-85

  Ghosh, Pavel ^a   Sen, Arunabha ^a   Hall, Alexander ^b  

^a Arizona State University   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MAPPING; BENCHMARK APPLICATIONS; CONSTANT FACTORS; ENERGY CONSUMPTION; ENERGY EFFICIENT; HETEROGENEOUS PROCESSING; HEURISTIC SOLUTIONS; MAPPING APPLICATIONS; MIXED INTEGER LINEAR PROGRAM; MULTIPLE VOLTAGE; NEAR-OPTIMAL SOLUTIONS; NETWORK ON CHIP; NP-HARD; OPTIMAL SOLUTIONS; PERFORMANCE CONSTRAINTS; PROCESSING ELEMENTS; RANDOMIZED ROUNDING; REAL APPLICATIONS; RESEARCH EFFORTS; SOLUTION TIME; SUB-PROBLEMS; UNIFIED APPROACH; VOLTAGE ASSIGNMENT;

BIOLOGICAL MATERIALS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; HEURISTIC METHODS; INTEGER PROGRAMMING; MAPPING; OPTIMAL SYSTEMS; OPTIMIZATION;

BENCHMARKING;

EID: 70349802415     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071448     Document Type: Conference Paper

References (9)

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