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Volumn 11, Issue 5, 2008, Pages 175-178

Silicon nanodot-array device with multiple gates

Author keywords

Coulomb blockade; Nanodot array; Single electron

Indexed keywords

CAPACITIVE COUPLINGS; DOT ARRAY; GATE VOLTAGES; LOGIC FUNCTIONS; MULTIPLE GATES; MULTIPLE INPUTS; NANO-DOT ARRAYS; NANODOT ARRAY; NANODOTS; NEW CONCEPT; PEAK SHIFT; SILICON ON INSULATOR WAFERS; SINGLE ELECTRON; SINGLE-ELECTRON DEVICES; STRUCTURAL CONFIGURATIONS;

EID: 70349779701     PISSN: 13698001     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mssp.2008.12.001     Document Type: Article
Times cited : (7)

References (12)
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  • 2
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  • 4
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    • Single-electron devices and their applications
    • Likharev K.K. Single-electron devices and their applications. Proc IEEE 87 4 (1999) 606-632
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  • 8
    • 0029206925 scopus 로고
    • Fabrication technique for Si single-electron transistor operating at room temperature
    • Takahashi Y., Nagase M., Namatsu H., Kurihara K., Iwadate K., Nakajima Y., et al. Fabrication technique for Si single-electron transistor operating at room temperature. Electron Lett 31 (1995) 136-137
    • (1995) Electron Lett , vol.31 , pp. 136-137
    • Takahashi, Y.1    Nagase, M.2    Namatsu, H.3    Kurihara, K.4    Iwadate, K.5    Nakajima, Y.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.