Test challenges for 3D circuits

Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium

Volumn 2006, Issue , 2006, Pages 79-

  Mak, T M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERCONNECTION NETWORKS; PROBLEM SOLVING; SILICON WAFERS; THREE DIMENSIONAL; TRANSISTORS;

CHIP LEVEL INTEGRATION; DIE STACKING; METAL INTERCONNECTS; WAFER THINNING;

MICROPROCESSOR CHIPS;

EID: 34247269196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2006.58     Document Type: Conference Paper

References (0)