3D technologies: Requiring more than 3 dimensions from concept to product

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 59-62

  Swinnen, B ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-DIMENSION; 3D TECHNOLOGY; DESIGN REQUIREMENTS; MATERIALS DEVELOPMENT; TECHNOLOGY ROADMAPPING;

SUPPLY CHAINS; TECHNOLOGICAL FORECASTING; THREE DIMENSIONAL;

TECHNOLOGY;

EID: 70349448675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090340     Document Type: Conference Paper

References (12)

1. E. Beyne, "Technologies for very high bandwidth electrical interconnects between next generation VLSI crcuits", IEEE-IEDM 2001 Technical digest, December 2-5, Washington D.C., S23-P3, 2001
2. E. Beyne, "3D interconnection and packaging: impending reality or still a dream?", IEEE ISSCC 2004, February 15-19, San Francisco, CA, pp. 138-148
3. Manuba Bonkohara, "Technologies for 3D assembly and chip level stack" Proceedings of 2nd International Symposium on Microelectronics and Packaging, ISMP2003, IMAPS-Korea, Seoul, Korea, September 24-25, 2003, pp.85-90.
4. K. W. Guarini, et al. "3D IC Technology: Capabilities and Applications"; proceedings "3D Architectures for Semiconductor Integration and packaging", RTI international, Burlingame, June 13-15, 2004.
5. A.Klump et al. "3D Integration of CMOS Transistors with ICV-SLID Technology"; proceedings "3D Architectures for Semiconductor Integration and packaging", RTI international, Burlingame, June 13-15, 2005.
6. McMahon J.J., Lu J.-Q., Gutmann R.J. (2005) "Wafer Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers for Via-First Three-Dimensional (3D) Interconnect" Proceeding of the 55th Electronic Components and Technology conference. IEEE, New Jersey, pp. 331 - 336
7. th Electronic Components and Technology conference. IEEE, New Jersey
8. th Electronic Components and Technology conference. IEEE, New Jersey
9. Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Ed. by P. Garrou, C. Bower, P. Ramm, 2008, Wiley
10. Wafer Level 3-D ICs Process Technology, Ed. by C. S. Tan, R. J. Gutmann, L. R. Reif, 2009, Springer
11. The International Technology Roadmap for Semiconductors, http://www.itrs.net/
12. Jisso: http://jisso.ipc.org/#