-
1
-
-
0030219216
-
Near Shannon limit performance of low density parity check codes
-
D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electron. Lett., vol. 32, no. 18, pp. 1645-1646, 1996.
-
(1996)
Electron. Lett
, vol.32
, Issue.18
, pp. 1645-1646
-
-
MacKay, D.J.C.1
Neal, R.M.2
-
2
-
-
0035246564
-
Factor graphs and the sum-product algorithm
-
Feb
-
F. Kschischang, B. Frey, and H. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 498-519, Feb 2001.
-
(2001)
IEEE Trans. Inform. Theory
, vol.47
, Issue.2
, pp. 498-519
-
-
Kschischang, F.1
Frey, B.2
Loeliger, H.3
-
3
-
-
0037421811
-
Iterative decoding using stochastic computation
-
Feb
-
V. Gaudet and A. Rapley, "Iterative decoding using stochastic computation," Electron. Lett., vol. 39, no. 3, pp. 299-301, Feb. 2003.
-
(2003)
Electron. Lett
, vol.39
, Issue.3
, pp. 299-301
-
-
Gaudet, V.1
Rapley, A.2
-
4
-
-
0036504121
-
A 690-mw 1-Gb/s 1024-b rate-1/2 low-density parity-check code decoder
-
March
-
A. Blanksby and C.J. Howland, "A 690-mw 1-Gb/s 1024-b rate-1/2 low-density parity-check code decoder," IEEE J. of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
-
(2002)
IEEE J. of Solid-State Circuits
, vol.37
, Issue.3
, pp. 404-412
-
-
Blanksby, A.1
Howland, C.J.2
-
5
-
-
48749115194
-
Block-interlaced LDPC decoders with reduced interconnect complexity
-
Jan
-
A. Darabiha, A. Chan Carusone, and F. R. Kschischang, "Block-interlaced LDPC decoders with reduced interconnect complexity," IEEE Trans. on Circuits and Systems-II: Express briefs, vol. 55, no. 1, pp. 74-78, Jan. 2008.
-
(2008)
IEEE Trans. on Circuits and Systems-II: Express briefs
, vol.55
, Issue.1
, pp. 74-78
-
-
Darabiha, A.1
Chan Carusone, A.2
Kschischang, F.R.3
-
6
-
-
54949135258
-
Fully parallel stochastic LDPC decoders
-
Nov
-
S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "Fully parallel stochastic LDPC decoders," IEEE Trans. on Signal Processing, vol. 56, no. 11, pp. 5692-5703, Nov. 2008.
-
(2008)
IEEE Trans. on Signal Processing
, vol.56
, Issue.11
, pp. 5692-5703
-
-
Sharifi Tehrani, S.1
Mannor, S.2
Gross, W.J.3
-
7
-
-
34548242432
-
Error-control decoders and probabilistic computation
-
Sendai, Japan, Oct
-
Chris Winstead, "Error-control decoders and probabilistic computation," in Tohoku Univ. 3rd SOIM-COE Conf., Sendai, Japan, Oct. 2005, pp. 349-352.
-
(2005)
Tohoku Univ. 3rd SOIM-COE Conf
, pp. 349-352
-
-
Winstead, C.1
-
8
-
-
33750049936
-
Stochastic decoding of LDPC codes
-
Oct
-
S. Sharifi Tehrani, W. J. Gross, and S. Mannor, "Stochastic decoding of LDPC codes," IEEE Comm. Lett., vol. 10, no. 10, pp. 716-718, Oct. 2006.
-
(2006)
IEEE Comm. Lett
, vol.10
, Issue.10
, pp. 716-718
-
-
Sharifi Tehrani, S.1
Gross, W.J.2
Mannor, S.3
-
9
-
-
54949142190
-
Stohastic decoding of linear block codes with high-densiy parity-check matrices
-
Nov
-
S. Sharifi Tehrani, C. Jego, B. Zhu, and W. J. Gross, "Stohastic decoding of linear block codes with high-densiy parity-check matrices," IEEE Trans. on Signal Processing, vol. 56, no. 11, pp. 5733-5739, Nov. 2008.
-
(2008)
IEEE Trans. on Signal Processing
, vol.56
, Issue.11
, pp. 5733-5739
-
-
Sharifi Tehrani, S.1
Jego, C.2
Zhu, B.3
Gross, W.J.4
-
10
-
-
47949120496
-
An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding
-
Shanghai, China, Oct
-
S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding," in Proc. of the IEEE Workshop on Signal Processing Systems (SiPS), Shanghai, China, Oct. 2007, pp. 255-260.
-
(2007)
Proc. of the IEEE Workshop on Signal Processing Systems (SiPS)
, pp. 255-260
-
-
Sharifi Tehrani, S.1
Mannor, S.2
Gross, W.J.3
|