-
1
-
-
33947411176
-
How GPUs work
-
Feb
-
D. Luebke and G. Humphreys, "How GPUs work," IEEE Comp., vol. 40, no. 2, pp. 96-100, Feb. 2007.
-
(2007)
IEEE Comp
, vol.40
, Issue.2
, pp. 96-100
-
-
Luebke, D.1
Humphreys, G.2
-
2
-
-
60649109040
-
Rise of the graphics processor
-
May
-
D. Blythe, "Rise of the graphics processor," Proc. IEEE, vol. 96, no. 5, pp. 761-778, May 2008.
-
(2008)
Proc. IEEE
, vol.96
, Issue.5
, pp. 761-778
-
-
Blythe, D.1
-
4
-
-
34748861928
-
A 33.2 M vertices/sec programmable geometry engine for multimedia embedded systems
-
May
-
C. H. Yu, D. Kim, and L.-S. Kim, "A 33.2 M vertices/sec programmable geometry engine for multimedia embedded systems," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005), May, vol. 5, pp. 4574-4577.
-
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2005)
, vol.5
, pp. 4574-4577
-
-
Yu, C.H.1
Kim, D.2
Kim, L.-S.3
-
5
-
-
0003935459
-
-
in C, 2nd ed. Reading, MA: Addison-Wesley
-
J. Foley, A. vanDam, S. Feiner, and J. Hughes, Computer Graphics: Principles and Practice in C, 2nd ed. Reading, MA: Addison-Wesley, 1995.
-
(1995)
Computer Graphics: Principles and Practice
-
-
Foley, J.1
vanDam, A.2
Feiner, S.3
Hughes, J.4
-
6
-
-
2442674217
-
A 109.5 mW 1.2 V 600 M texels/s 3-D graphics engine
-
M. Imai, T. Nagasaki, J. Sakamoto, H. Takeuchi, H. Nagano, S. Iwasakii, M. Hatakenaka, J. Fujita, K. Keino, T. Motomura, T. Ueda, T. Niki, and H. Tomikawa, "A 109.5 mW 1.2 V 600 M texels/s 3-D graphics engine," in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2004), vol. 1, pp. 332-333.
-
Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2004)
, vol.1
, pp. 332-333
-
-
Imai, M.1
Nagasaki, T.2
Sakamoto, J.3
Takeuchi, H.4
Nagano, H.5
Iwasakii, S.6
Hatakenaka, M.7
Fujita, J.8
Keino, K.9
Motomura, T.10
Ueda, T.11
Niki, T.12
Tomikawa, H.13
-
7
-
-
28144453988
-
An SoC with 1.3 Gtexels/s 3D graphics full pipeline engine for consumer applications
-
D. Kim, "An SoC with 1.3 Gtexels/s 3D graphics full pipeline engine for consumer applications," in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2005), pp. 190-192.
-
Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2005)
, pp. 190-192
-
-
Kim, D.1
-
8
-
-
28144454580
-
A 50 M vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications
-
J.-H. Sohn, J.-H. Woo, M.-W Lee, H.-J Kim, R. Woo, and. H.-J. Yoo, "A 50 M vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications," in Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2005), pp. 192-592.
-
Proc. IEEE Int. Solid State Circuits Conf. (ISSCC 2005)
, pp. 192-592
-
-
Sohn, J.-H.1
Woo, J.-H.2
Lee, M.-W.3
Kim, H.-J.4
Woo, R.5
Yoo, H.-J.6
-
9
-
-
33750808634
-
A 231 MHz, 2.18 mW 32-bit logarithmic aritmetic unit for fixed-point 3-D graphics system
-
Nov
-
H. Kim, B. Nam, J. Sohn, J.Woo, and H. Yoo, "A 231 MHz, 2.18 mW 32-bit logarithmic aritmetic unit for fixed-point 3-D graphics system," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2373-2381, Nov. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.11
, pp. 2373-2381
-
-
Kim, H.1
Nam, B.2
Sohn, J.3
Woo, J.4
Yoo, H.5
-
10
-
-
34547436736
-
A low-power unified arithmetic unit for programmable handheld 3-D graphics system
-
Aug
-
B. Nam, H. Kim, and H. Yoo, "A low-power unified arithmetic unit for programmable handheld 3-D graphics system," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1767-1778, Aug. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.8
, pp. 1767-1778
-
-
Nam, B.1
Kim, H.2
Yoo, H.3
-
11
-
-
0034228634
-
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing
-
July
-
N. Ide, "2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1025-1033, July 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.7
, pp. 1025-1033
-
-
Ide, N.1
-
13
-
-
20344381571
-
The GeForce 6800
-
Mar./Apr
-
J. Montrym and H. Moreton, "The GeForce 6800," IEEE Micro, vol. 25, no. 2, pp. 41-51, Mar./Apr. 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 41-51
-
-
Montrym, J.1
Moreton, H.2
-
14
-
-
49049088756
-
GPU computing
-
May
-
J. D. Owens, M. Houston, D. Luebke, S. Green, J. E. Stone, and J. C. Phillips, "GPU computing," Proc. IEEE, vol. 96, no. 5, pp. 879-899, May 2008.
-
(2008)
Proc. IEEE
, vol.96
, Issue.5
, pp. 879-899
-
-
Owens, J.D.1
Houston, M.2
Luebke, D.3
Green, S.4
Stone, J.E.5
Phillips, J.C.6
-
16
-
-
14844347965
-
High-speed function approximation using a minimax quadratic interpolator
-
Mar
-
J. A. Pineiro, S. F. Oberman, J. M. Muller, and J. D. Bruguera, "High-speed function approximation using a minimax quadratic interpolator," IEEE Trans. Comp., vol. 54, no. 3, pp. 304-318, Mar. 2005.
-
(2005)
IEEE Trans. Comp
, vol.54
, Issue.3
, pp. 304-318
-
-
Pineiro, J.A.1
Oberman, S.F.2
Muller, J.M.3
Bruguera, J.D.4
-
17
-
-
14844344080
-
Multipartite table methods
-
Mar
-
F. De Dinechin and A. Tisserand, "Multipartite table methods," IEEE Trans. Comput., vol. 54, no. 3, pp. 319-330, Mar. 2005.
-
(2005)
IEEE Trans. Comput
, vol.54
, Issue.3
, pp. 319-330
-
-
De Dinechin, F.1
Tisserand, A.2
-
20
-
-
30344472982
-
Optimizing hardware function evaluation
-
Dec
-
D. U. Lee, A. A. Gaffar, O. Mencer, and W. Luk, "Optimizing hardware function evaluation," IEEE Trans. Comput., vol. 45, no. 12, pp. 1520-1531, Dec. 2005.
-
(2005)
IEEE Trans. Comput
, vol.45
, Issue.12
, pp. 1520-1531
-
-
Lee, D.U.1
Gaffar, A.A.2
Mencer, O.3
Luk, W.4
-
21
-
-
0033222011
-
A senventh-generation x86 microprocessor
-
Nov
-
M. Golden, "A senventh-generation x86 microprocessor," IEEE J. Solid-State Circuits, vol. 34, no. 11, pp. 1466-1477, Nov. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.11
, pp. 1466-1477
-
-
Golden, M.1
-
22
-
-
0035301218
-
A hardware cost minimized fast phong shader
-
Apr
-
H. C. Shin, J. A. Lee, and L. S. Kim, "A hardware cost minimized fast phong shader," IEEE Trans. Very Large Scale Integr. (VLSI) Systems vol. 9, no. 2, pp. 297-304, Apr. 2001.
-
(2001)
IEEE Trans. Very Large Scale Integr. (VLSI) Systems
, vol.9
, Issue.2
, pp. 297-304
-
-
Shin, H.C.1
Lee, J.A.2
Kim, L.S.3
-
23
-
-
0028485284
-
Hardware design for exactly rounded elementary functions
-
Aug
-
M. J. Schulte and E. E. Swartzlander, "Hardware design for exactly rounded elementary functions," IEEE Trans. Comput., vol. 43, no. 8, pp. 964-973, Aug. 1994.
-
(1994)
IEEE Trans. Comput
, vol.43
, Issue.8
, pp. 964-973
-
-
Schulte, M.J.1
Swartzlander, E.E.2
-
24
-
-
0034866183
-
High-performance architectures for elementary function generation
-
J. Cao, B. Wei, and J. Cheng, "High-performance architectures for elementary function generation," in Proc. 15th Symp. Computer Arithmetic (ARITH15), 2001, pp. 136-144.
-
(2001)
Proc. 15th Symp. Computer Arithmetic (ARITH15)
, pp. 136-144
-
-
Cao, J.1
Wei, B.2
Cheng, J.3
-
25
-
-
33845572284
-
Compact numerical function generators based on quadratic approximation: Architecture and synthesis method
-
Dec
-
S. Nagayama, T. Sasao, and J. T. Butler, "Compact numerical function generators based on quadratic approximation: Architecture and synthesis method," IEICE Trans. Fundam., vol. E89-A, no. 12, Dec. 2006.
-
(2006)
IEICE Trans. Fundam
, vol.E89-A
, Issue.12
-
-
Nagayama, S.1
Sasao, T.2
Butler, J.T.3
-
27
-
-
36349023943
-
Theoretical upper bound of the spurious free dynamic range in direct digital frequency synthesizers realized by polynomial interpolation methods
-
Oct
-
A. Ashrafi and R. Adhami, "Theoretical upper bound of the spurious free dynamic range in direct digital frequency synthesizers realized by polynomial interpolation methods," IEEE Trans. Circuit Syst., vol. 54, no. 10, pp. 2252-2261, Oct. 2007.
-
(2007)
IEEE Trans. Circuit Syst
, vol.54
, Issue.10
, pp. 2252-2261
-
-
Ashrafi, A.1
Adhami, R.2
-
28
-
-
33746876981
-
Dual-tree error compensation for high performance fixed-width multipliers
-
Aug
-
A. G. M. Strollo, N. Petra, and D. De Caro, "Dual-tree error compensation for high performance fixed-width multipliers," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 8, pp. 501-507, Aug. 2005.
-
(2005)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.52
, Issue.8
, pp. 501-507
-
-
Strollo, A.G.M.1
Petra, N.2
De Caro, D.3
-
29
-
-
0032495361
-
VLSI implementation of a 350 MHz 0.35 micron 8 bit merged squarer
-
R. K. Kolagotla, W. R. Griesbach, and H. R. Srinivas, "VLSI implementation of a 350 MHz 0.35 micron 8 bit merged squarer," Electron. Lett., vol. 34, no. 1, pp. 47-48, 1998.
-
(1998)
Electron. Lett
, vol.34
, Issue.1
, pp. 47-48
-
-
Kolagotla, R.K.1
Griesbach, W.R.2
Srinivas, H.R.3
-
30
-
-
0033325078
-
Combined unsigned and two's complement squarers
-
K. E.Wires, M. J. Shulte, L. P. Marquette, and P. Balzola, "Combined unsigned and two's complement squarers," in Proc. Asilomar Conf. Signals, Syst. Comput., 1999, pp. 125-1219.
-
(1999)
Proc. Asilomar Conf. Signals, Syst. Comput
, pp. 125-1219
-
-
Wires, K.E.1
Shulte, M.J.2
Marquette, L.P.3
Balzola, P.4
-
31
-
-
31344446201
-
An SoC with 1.3 Gtexels/s 3-D graphics full pipeline for consumer applications
-
Jan
-
D. Kim, "An SoC with 1.3 Gtexels/s 3-D graphics full pipeline for consumer applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 71-82, Jan. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.1
, pp. 71-82
-
-
Kim, D.1
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