A wideband PLL-based G/FSK transmitter in 0.18 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 9, 2009, Pages 2452-2462

  Liu, Yao Hong ^a   Lin, Tsung Hsien ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

; Direct Digital frequency synthesis (DDFS); Flying adder; Fractional frequency divider; Fractional N; FSK transmitters; Multiphase PLL; Phase locked loops (PLL); Sigma delta

Indexed keywords

DIRECT DIGITAL FREQUENCY SYNTHESIS (DDFS); FLYING-ADDER; FRACTIONAL FREQUENCY DIVIDER; FRACTIONAL-N; FSK TRANSMITTERS; MULTIPHASE PLL; PHASE-LOCKED LOOPS (PLL); SIGMA-DELTA;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DELTA SIGMA MODULATION; ENERGY EFFICIENCY; FREQUENCY DIVIDING CIRCUITS; FREQUENCY SHIFT KEYING; PHASE TRANSITIONS; SPURIOUS SIGNAL NOISE; TRANSMITTERS;

PHASE LOCKED LOOPS;

EID: 70249097324     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2022994     Document Type: Article

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