Porous silicon for the development of capacitive microstructures

Microelectronic Engineering

Volumn 86, Issue 11, 2009, Pages 2144-2148

  Sancho, A ^a   Arizti, F ^a   Gracia, F J ^a  

^a CEIT   (Spain)

Author keywords

Capacitance; Electrochemistry; HARS; Porous silicon; Surface enlargement

Indexed keywords

3D ARCHITECTURES; ACTIVE SURFACE AREA; CAPACITANCE DENSITY; CAPACITIVE DEVICES; CAPACITIVE ELEMENTS; ELECTRICAL BEHAVIORS; EQUIVALENT ELECTRICAL CIRCUITS; HARS; LOW FREQUENCY; MACRO POROUS SILICON; P-TYPE SUBSTRATES; POLY-SI;

CAPACITANCE; ELECTROCHEMISTRY; MICROSTRUCTURE; TWO DIMENSIONAL;

POROUS SILICON;

EID: 69549135463     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.02.031     Document Type: Article

References (12)

1. Sun W., Puzas J.E., Sheu T.J., and Fauchet P.M. Phys. Status Solidi (a) 204 5 (2007) 1429
2. Fauchet P.M. J. Lumin. 80 (1998) 53
3. Gerritsen E., et al. Solid State Electron. 49 (2005) 1767
4. Sancho A., Etxeberria J.A., and Gracia F.J. Microelectron. Eng. 84 (2007) 1308
5. Sancho A., Pérez N., and Gracia F.J. Phys. Status Solidi (c) 5 11 (2008) 3471
6. Steiner P., and Lang W. Thin Solid Films 255 (1995) 52
7. Tao Y., and Esashi M. J. Micromech. Microeng. 14 (2004) 1411
8. Kaltsas G., and Nassiopoulou A.G. Sens. Actuators B 76 (2001)
9. Riekkinen T., and Molarius J. Microelectron. Eng. 70 (2003) 392
10. Dueñas S., et al. J. Mater. Sci. Mater. Electron. 10 (1999) 379
11. Farcy A., et al. Microelectron. Eng. 70 (2003) 368
12. Roozeboom F., et al. Microelectron. Eng. 53 (2000) 581