Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities

Microelectronics Reliability

Volumn 49, Issue 9-11, 2009, Pages 1008-1012

  Bénard, Christelle ^a,c   Math, Gaëtan ^a,c   Fornara, Pascal ^a   Ogier, Jean Luc ^a   Goguenheim, Didier ^b,c  

^a STMICROELECTRONICS   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

^c CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BULK DOPING; FORMING GAS; INTERFACE STATE; NBTI LIFETIME; NEGATIVE BIAS TEMPERATURE INSTABILITY; OXIDE THICKNESS; PMOSFET'S; PROCESS STEPS; STRESS CONDITION; THERMAL ANNEALS;

ARSENIC; FLUORINE; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; THERMODYNAMIC STABILITY;

PHASE INTERFACES;

EID: 69349091117     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2009.06.022     Document Type: Article

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