-
1
-
-
84989495069
-
Timing verification and the timing analysis program
-
R. Hitchcock, "Timing verification and the timing analysis program," in Proc. DAC, 1982, pp. 594-604.
-
(1982)
Proc. DAC
, pp. 594-604
-
-
Hitchcock, R.1
-
2
-
-
0027614893
-
Statistical timing analysis of combinational logic circuits
-
Jun.
-
H.-F. Jyu, S. Malik, S. Devadas, and K. W. Keutzer, "Statistical timing analysis of combinational logic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 2, pp. 126-137, Jun. 1993.
-
(1993)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.1
, Issue.2
, pp. 126-137
-
-
Jyu, H.-F.1
Malik, S.2
Devadas, S.3
Keutzer, K.W.4
-
3
-
-
0041633575
-
Statistical timing for parametric yield prediction of digital integrated circuits
-
J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," in Proc. DAC, 2003, pp. 932-937.
-
(2003)
Proc. DAC
, pp. 932-937
-
-
Jess, J.A.G.1
Kalafala, K.2
Naidu, S.R.3
Otten, R.H.J.M.4
Visweswariah, C.5
-
5
-
-
84949959155
-
Timing yield estimation for static timing analysis
-
A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation for static timing analysis," in Proc. ISQED, 2001, pp. 437-442.
-
(2001)
Proc. ISQED
, pp. 437-442
-
-
Gattiker, A.1
Nassif, S.2
Dinakar, R.3
Long, C.4
-
6
-
-
0041633857
-
Computational and refinement of statistical bounds on circuit delay
-
A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computational and refinement of statistical bounds on circuit delay," in Proc. DAC, 2003, pp. 348-353.
-
(2003)
Proc. DAC
, pp. 348-353
-
-
Agarwal, A.1
Blaauw, D.2
Zolotov, V.3
Vrudhula, S.4
-
7
-
-
0348040110
-
Block-based static timing analysis with uncertainty
-
A. Devgan and C. Kashyap, "Block-based static timing analysis with uncertainty," in Proc. ICCAD, 2003, pp. 607-614.
-
(2003)
Proc. ICCAD
, pp. 607-614
-
-
Devgan, A.1
Kashyap, C.2
-
8
-
-
0346778721
-
Statistical timing analysis considering spatial correlations using a single PERT-like traversal
-
H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. ICCAD, 2003, pp. 621-625.
-
(2003)
Proc. ICCAD
, pp. 621-625
-
-
Chang, H.1
Sapatnekar, S.2
-
9
-
-
0036049629
-
General probabilistic framework for worst-case timing analysis
-
M. Orshansky and K. Keutzer, "General probabilistic framework for worst-case timing analysis," in Proc. DAC, 2002, pp. 556-561.
-
(2002)
Proc. DAC
, pp. 556-561
-
-
Orshansky, M.1
Keutzer, K.2
-
10
-
-
0018467641
-
Probabilistic PERT
-
A. Nadas, "Probabilistic PERT," IBM J. Res. Develop., vol. 23, no. 3, pp. 339-347, 1979.
-
(1979)
IBM J. Res. Develop.
, vol.23
, Issue.3
, pp. 339-347
-
-
Nadas, A.1
-
13
-
-
0034429814
-
Delay variability: Sources, impact and trends
-
S. Nassif, "Delay variability: Sources, impact and trends," in Proc. Int. Solid-State Circuits Conf., 2000, pp. 368-369.
-
(2000)
Proc. Int. Solid-state Circuits Conf.
, pp. 368-369
-
-
Nassif, S.1
-
14
-
-
4444233012
-
First-order incremental block-based statistical timing analysis
-
C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in Proc. DAC, 2004, pp. 331-336.
-
(2004)
Proc. DAC
, pp. 331-336
-
-
Visweswariah, C.1
Ravindran, K.2
Kalafala, K.3
Walker, S.G.4
Narayan, S.5
-
15
-
-
0024889867
-
Efficient algorithms for extracting the k most critical paths in timing analysis
-
S. Yen, D. Du, and S. Ghanta, "Efficient algorithms for extracting the k most critical paths in timing analysis," in Proc. DAC, 1989, pp. 649-652.
-
(1989)
Proc. DAC
, pp. 649-652
-
-
Yen, S.1
Du, D.2
Ghanta, S.3
-
16
-
-
0026175373
-
Incremental techniques for the identification of statically sensitizable critical paths
-
Y.-C. Ju and R. Saleh, "Incremental techniques for the identification of statically sensitizable critical paths," in Proc. DAC, 1991, pp. 541-546.
-
(1991)
Proc. DAC
, pp. 541-546
-
-
Ju, Y.-C.1
Saleh, R.2
|