메뉴 건너뛰기




Volumn 16, Issue 6, 2009, Pages 513-516

Efficient hardware implementations of low bit depth motion estimation algorithms

Author keywords

Low bit depth motion estimation; Motion estimation hardware; Source pixel based linear arrays

Indexed keywords

BIT DEPTH; BLOCK MEMORIES; DATA FLOW; FULL SEARCH; HARDWARE ARCHITECTURE; HARDWARE IMPLEMENTATIONS; LOW BIT-DEPTH MOTION ESTIMATION; MOTION ESTIMATION ALGORITHM; NUMBER OF DATUM; ONE BIT TRANSFORM; POWER CONSUMPTION; REAL TIME VIDEOS; SOURCE PIXEL BASED LINEAR ARRAYS;

EID: 68949166943     PISSN: 10709908     EISSN: None     Source Type: Journal    
DOI: 10.1109/LSP.2009.2017222     Document Type: Article
Times cited : (34)

References (13)
  • 2
    • 33847626606 scopus 로고    scopus 로고
    • Multiplication-free one-bit transform, for low-complexity block-based motion, estimation
    • Feb
    • S. Ertürk, "Multiplication-free one-bit transform, for low-complexity block-based motion, estimation," IEEE Signal Process. Lett., vol. 14, no. 2, pp. 109-112, Feb. 2007.
    • (2007) IEEE Signal Process. Lett. , vol.14 , Issue.2 , pp. 109-112
    • Ertürk, S.1
  • 3
    • 39549108327 scopus 로고    scopus 로고
    • Early termination scheme for binary block motion estimation
    • Nov
    • H. Lee and J. Jeong, "Early termination scheme for binary block motion estimation," IEEE Trans. Consumer Electron., vol. 53, no. 4, pp. 1682-1686, Nov. 2007.
    • (2007) IEEE Trans. Consumer Electron. , vol.53 , Issue.4 , pp. 1682-1686
    • Lee, H.1    Jeong, J.2
  • 4
    • 23744490030 scopus 로고    scopus 로고
    • Two-bit transform for binary block motion estimation
    • Jul
    • A. Ertürk and S. Erẗrk, "Two-bit transform for binary block motion estimation," IEEE Trans. Circuits Syst. Video Technol, vol. 15, no. 7, pp. 938-946, Jul. 2005.
    • (2005) IEEE Trans. Circuits Syst. Video Technol , vol.15 , Issue.7 , pp. 938-946
    • Ertürk, A.1    Erẗrk, S.2
  • 5
    • 34247566544 scopus 로고    scopus 로고
    • Constrained one-bit transform for low complexity block motion estimation
    • Apr
    • O. Urhan and S. Ertürk, "Constrained one-bit transform for low complexity block motion estimation," IEEE Trans. Circuits Syst. Video Technol, vol. 17, no. 4, pp. 478-482, Apr. 2007.
    • (2007) IEEE Trans. Circuits Syst. Video Technol , vol.17 , Issue.4 , pp. 478-482
    • Urhan, O.1    Ertürk, S.2
  • 7
    • 0036687994 scopus 로고    scopus 로고
    • A novel all-binary motion estimation (ABME) with optimized hardware architectures
    • Aug
    • J.-H. Luo, C.-N. Wang, and T. Chiang, "A novel all-binary motion estimation (ABME) with optimized hardware architectures," IEEE Trans. Circuits Syst. Video Technol, vol. 12, no. 8, pp. 700-712, Aug. 2002.
    • (2002) IEEE Trans. Circuits Syst. Video Technol , vol.12 , Issue.8 , pp. 700-712
    • Luo, J.-H.1    Wang, C.-N.2    Chiang, T.3
  • 8
    • 33746887055 scopus 로고    scopus 로고
    • A high performance hardware architecture for an SAD reuse based hierarchical motion, estimation algorithm for H.264 video coding
    • Aug
    • S. Yalcin, H. Ates, and I. Hamzaoglu, "A high performance hardware architecture for an SAD reuse based hierarchical motion, estimation algorithm for H.264 video coding," in Int. Conf. on Field Programmable Logic and Applications, Aug. 2005, pp. 509-514.
    • (2005) Int. Conf. on Field Programmable Logic and Applications , pp. 509-514
    • Yalcin, S.1    Ates, H.2    Hamzaoglu, I.3
  • 10
    • 34247556136 scopus 로고    scopus 로고
    • Fast algorithm, and architecture design of low-power integer motion estimation for H.264/AVC
    • May
    • T.-C. Chen, Y.-H. Chen, S.-F. Tsai, S.-Y. Chien, and L.-G. Chen, "Fast algorithm, and architecture design of low-power integer motion estimation for H.264/AVC," IEEE Trans. Circuits Syst. Video Technol, vol. 17, no. 5, pp. 568-577, May 2007.
    • (2007) IEEE Trans. Circuits Syst. Video Technol , vol.17 , Issue.5 , pp. 568-577
    • Chen, T.-C.1    Chen, Y.-H.2    Tsai, S.-F.3    Chien, S.-Y.4    Chen, L.-G.5
  • 11
    • 48749121983 scopus 로고    scopus 로고
    • Memory bandwidth efficient hardware architecture for AVS encoder
    • May
    • D. Ding, S. Yao, and L. Yu, "Memory bandwidth efficient hardware architecture for AVS encoder," IEEE Trans. on Consumer Electron., vol. 54, no. 2, pp. 675-680, May 2008.
    • (2008) IEEE Trans. on Consumer Electron. , vol.54 , Issue.2 , pp. 675-680
    • Ding, D.1    Yao, S.2    Yu, L.3
  • 12
    • 54349087852 scopus 로고    scopus 로고
    • A high-performance reconfigurable VLSI architecture for VBSME in H.264
    • Aug
    • C. Wei, H. Hui, T. Jiarong, and M. Hao, "A high-performance reconfigurable VLSI architecture for VBSME in H.264," IEEE Trans. Consumer-Electron., vol. 54, no. 3, pp. 1338-1345, Aug. 2008.
    • (2008) IEEE Trans. Consumer-Electron. , vol.54 , Issue.3 , pp. 1338-1345
    • Wei, C.1    Hui, H.2    Jiarong, T.3    Hao, M.4
  • 13
    • 48749092019 scopus 로고    scopus 로고
    • Low power H.264 deblocking filter hardware implementations
    • May
    • M. Parlak and I. Hamzaoglu, "Low power H.264 deblocking filter hardware implementations," IEEE Trans. Consumer Electron., vol. 54, no. 2, May 2008.
    • (2008) IEEE Trans. Consumer Electron. , vol.54 , Issue.2
    • Parlak, M.1    Hamzaoglu, I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.