Memory bandwidth efficient hardware architecture for AVS encoder

IEEE Transactions on Consumer Electronics

Volumn 54, Issue 2, 2008, Pages 675-680

  Ding, Dandan ^a   Yao, Shuo ^a   Yu, Lu ^a  

^a ZHEJIANG UNIVERSITY   (China)

Author keywords

Bandwidth; Bit rate; Hardware; Memory management; Motion estimation; Pixel; System on a chip

Indexed keywords

LOGIC DEVICES; MOTION ESTIMATION; PROGRAMMING THEORY; SULFATE MINERALS; TELECOMMUNICATION SYSTEMS;

CODING PERFORMANCE; CONTROL MECHANISMS; DATA REUSING; EFFICIENT ARCHITECTURE; HARDWARE ARCHITECTURE (GRAPHICS PROCESSORS); MEMORY BANDWIDTHS; MEMORY CONSUMPTION; ON CHIP MEMORIES;

BANDWIDTH;

EID: 48749121983     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2008.4560146     Document Type: Article

References (9)

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