A high-performance reconfigurable VLSI architecture for VBSME in H.264

IEEE Transactions on Consumer Electronics

Volumn 54, Issue 3, 2008, Pages 1338-1345

  Wei, Cao ^a   Hui, Hou ^a   Jiarong, Tong ^a   Jinmei, Lai ^a   Hao, Min ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

H.264; Motion estimation; Reconfigurable architecture; VBSME; VLSI

Indexed keywords

ARCHITECTURE; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; MOTION PICTURE EXPERTS GROUP STANDARDS; PARALLEL PROCESSING SYSTEMS;

AVC/H.264; CLOCK FREQUENCIES; CMOS TECHNOLOGIES; COMPUTING ARRAYS; DATA FLOWS; DATA REUSES; FULL SEARCH BLOCK MATCHING; H.264; HARDWARE UTILIZATIONS; HIGH-PERFORMANCE; MOTION VECTORS; PROCESSING ELEMENTS; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE COMPUTING ARRAYS; RECONFIGURABLE VLSI ARCHITECTURES; SEARCH AREAS; SEARCH RANGES; TIME PROCESSING; VARIABLE BLOCK SIZE MOTION ESTIMATIONS; VBSME; VLSI;

MOTION ESTIMATION;

EID: 54349087852     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2008.4637625     Document Type: Article

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