Low power H.264 deblocking filter hardware implementations

IEEE Transactions on Consumer Electronics

Volumn 54, Issue 2, 2008, Pages 808-816

  Parlak, Mustafa ^a   Hamzaoglu, Ilker ^a  

^a SABANCI UNIVERSITY   (Turkey)

Author keywords

Deblocking Filter; FPGA; H.264; Hardware Implementation; Low Power; Video Coding

Indexed keywords

COST EFFECTIVENESS; DECODING; ELECTRIC BATTERIES; ELECTRIC FILTERS; ELECTRIC POWER UTILIZATION; HARDWARE; MOTION ESTIMATION; PORTABLE EQUIPMENT; STANDARDS; WAVE FILTERS;

COST EFFECTIVE SOLUTIONS; ENCODER/DECODER; FRAMES PER SECOND (FPS); GATE COUNTS; H.264 DEBLOCKING FILTER; H.264 VIDEO ENCODER; HARDWARE ARCHITECTURE (GRAPHICS PROCESSORS); HARDWARE IMPLEMENTATIONS; LOW POWERS; MACRO BLOCK (MB); ON CHIP MEMORIES; PORTABLE APPLICATIONS; POWER CONSUMPTION (CE); STANDARD-CELL LIBRARIES; VERILOG HDL; XILINX VIRTEX II FPGA;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 48749092019     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2008.4560164     Document Type: Article

References (13)

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