Loss reduction of Si wire waveguide fabricated by edge-enhancement writing for electron beam lithography and reactive ion etching using double layered resist mask with C60

Japanese Journal of Applied Physics

Volumn 48, Issue 3, 2009, Pages 030208-

  Inoue, Keita ^a   Plumwongrot, Dhanorm ^a,c   Nishiyama, Nobuhiko ^a,d   Sakamoto, Shinichi ^a   Enomoto, Haruki ^a   Tamura, Shigeo ^a   Maruyama, Takeo ^a,b   Arai, Shigehisa ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b KANAZAWA UNIVERSITY   (Japan)

^c FURUKAWA ELECTRIC CO LTD   (Japan)

^d FUJIKURA LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

1550 NM; CORE SIZE; DOUBLE LAYERED; DOUBLE LAYERS; EDGE ENHANCEMENTS; ELECTRON BEAM RESIST; LOSS REDUCTION; PARALLEL PLATES; PHOTONIC WIRES; SI WIRE WAVEGUIDE; SILICON ON INSULATOR; SINGLE MODE; TRANSVERSE ELECTRIC MODES;

DRY ETCHING; ELECTRIC LOSSES; ELECTRON BEAM LITHOGRAPHY; ELECTRON BEAMS; FABRICATION; PLASMA ETCHING; SILICON; WAVEGUIDES; WIRE;

REACTIVE ION ETCHING;

EID: 67650844756     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.48.030208     Document Type: Article

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