Investigation of error floors of structured low-density parity-check codes by hardware emulation

GLOBECOM - IEEE Global Telecommunications Conference

Volumn , Issue , 2006, Pages

  Zhengya, Zhang ^a   Dolecek, Lara ^a   Nikolić, Borivoje ^a   Anantharam, Venkat ^a   Wainwright, Martin ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DECODING; ERROR DETECTION;

FIXED-POINT DECODERS; HARDWARE EMULATION; LOW-DENSITY PARITY-CHECK CODES (LDPC); PERMUTATION SUBMATRICES;

REED-SOLOMON CODES;

EID: 50949097623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2006.160     Document Type: Conference Paper

References (12)

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