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Volumn 60, Issue 4, 2004, Pages 2549-2553
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Lowering the error floors of irregular high-rate LDPC codes by graph conditioning
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Author keywords
[No Author keywords available]
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Indexed keywords
INFORMATION-NULLING TECHNIQUE;
IRREGULAR REPEAT-ACCUMULATE (IRA) CODES;
LOW DENSITY PARITY CHECK (LDPC) CODES;
SHANNON LIMIT;
ALGORITHMS;
BIT ERROR RATE;
COMMUNICATION CHANNELS (INFORMATION THEORY);
CONSTRAINT THEORY;
ERRORS;
GAUSSIAN NOISE (ELECTRONIC);
GRAPH THEORY;
MATRIX ALGEBRA;
OPTIMIZATION;
SIGNAL TO NOISE RATIO;
TURBO CODES;
WHITE ACOUSTIC NOISE;
CODES (SYMBOLS);
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EID: 17144375253
PISSN: 15502252
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (19)
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References (7)
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