Overcoming the memory wall in packet processing: Hammers or ladders?

2005 Symposium on Architectures for Networking and Communications Systems, ANCS 2005

Volumn , Issue , 2005, Pages 1-10

  Mudigonda, Jayaram ^a   Vin, Harrick M ^a   Yavatkar, Raj ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Data caches; Multithreading; Network processors

Indexed keywords

DATA-CACHES; HARDWARE DESIGN; HARDWARE MECHANISM; MEMORY ACCESS; MEMORY WALL; MULTITHREADING; NETWORK PROCESSOR; NETWORK PROCESSORS; OFF-CHIP MEMORIES; PACKET PROCESSING; PACKET THROUGHPUT; PROGRAMMABILITY; SINGLE MECHANISMS; SYSTEM RESOURCES;

CIRCUIT THEORY; MACHINE DESIGN; MULTITASKING; PACKET NETWORKS;

CACHE MEMORY;

EID: 67650378970     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ANCS.2005.4675260     Document Type: Conference Paper

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