Architectural Analysis and Instruction-Set Optimization for Design of Network Protocol Processors

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2003, Pages 225-230

  Xie, Haiyong ^a   Zhao, Li ^a   Bhuyan, Laxmi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architecture simulation; Instruction optimization; Network processing; TCP IP protocol

Indexed keywords

ARCHITECTURE SIMULATION; INSTRUCTION OPTIMIZATION; NETWORK PROCESSING; TCP/IP PROTOCOL;

BANDWIDTH; CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; COMPUTER SIMULATION; COMPUTER SYSTEMS; DATA STRUCTURES; DECODING; EMBEDDED SYSTEMS; INTERNET; MULTIPROCESSING PROGRAMS; PACKET NETWORKS; PROGRAM PROCESSORS; REAL TIME SYSTEMS; TELECOMMUNICATION TRAFFIC;

NETWORK PROTOCOLS;

EID: 1142275610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/944645.944703     Document Type: Conference Paper

References (21)

1. Boon S. Ang. An Evaluation of an Attempt at Offloading TCP/IP Protocol Processing onto an i960RN-based iNIC. HP Labs Technical Report HPL-2001-8, January 2001
2. M. Benz. An Architecture and Prototype Implementation for TCP/IP Hardware Support. TERENA Networking Conference 2001, Turkey, May 2001
3. Trevor Blackwell. Speeding Up Protocols for Small Messages. ACM SIGCOMM Symposium on Communications Architectures and Protocols, 1996
4. Ross Gallon. Predictions for the Core of the Network. IEEE Internet Computing, 4(1), February 2000
5. Cisco CSS 11000 series content services switches, http://www.cisco.com/warp/public/cc/pd/si/11000/
6. Ethereal Network Analyzer, http://www.ethereal.com
7. Foundry Networks, Inc. BigIron, http://www.foundrynet.com/products/13backbone/bigiron/
8. A. Gallatin, J. Chase, K. Yocum. Trapeze/IP: TCP/IP at Near-Gigabit Speeds. USENIX Technical Conference, June 1999
9. T. Halfhill. Intel Network Processor Targets Routers. Microprocessor Report, September 1999
10. Norman Hutchingson, and Larry Peterson. The x-kernel: An Architecture for implementing network protocols. IEEE Transactions on Software Engineering, 17(1):64-76, January 1991
11. J. Kay and J. Pasquale. The Importance of Non-Data Touching Processing Overheads in TCP/IP. Proceedings of the SIGCOMM '93 Symposium on Communications Architectures and Protocols, September 1993.
12. J. Kay and J. Pasquale. Profiling and reducing processing overheads in TCP/IP. IEEE/ACM Transactions on Networking, Vol. 4, No. 6, December 1996
13. K. Krewell. Rainier Leads PowerNP Family. Microprocessor Report, January 2001
14. M.K. McKusick, K. Bostic, M.J. Karels, and J.S. Quarterman. The Design and Implementation of the 4.4BSD Unix Operating System. Adison-Wesley Publishing Company, MA, 1996
15. D. Mosberger, L.L. Peterson, P.O. Bridges, and S. O'Malley. Analysis of Techniques to Improve Protocol Processing Latency. Proceedings of SIGCOMM '91 Symposium on Communication Architectures and Protocols, 1996
16. E. Nahum, D. Yates, J. Kurose, and D. Towsley. Cache Behavior of Network Protocols. SIGMETRICS, 1997
17. SimpleScalar LLC, http://www.simplescalar.com
18. Jonathan M. Smith. Seleted Challenges in Computer Networking. IEEE Computer, 32(1), Jan 1999
19. Standard Performance Evaluation Corporation, SPEC CPU 2000 Version 1.2, December 7, 2001
20. K. Thompson, G. Miller, and R. Wilder. Wide Area Internet Traffic Patterns and Characteristics. IEEE Network, 11(6):10-23, November 1997
21. T. Wolf and M. Franklin. Commbench: A Telecommunications Benchmark for Network Processors. IEEE International Symposium on Performance Analysis of Systems and Software, April 2000